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TAU
(Tape Adapter Unit)

Subject: Re: CE Manual for TAU 9 - Date: August 30, 2019

My memory tells me... The TAU A-reg only captures high confidence read characters. (A high compare threshold is used in signal detection.) The TAU B-reg is more permissive and attempts to capture weaker read characters. (A low compare threshold is used in signal detection.) On Tape Write operations, the TAU demands that confidence data was written. VRC errors are reported if the A-reg does not have good parity (all written Ones show a strong flux change); and Comp errors are reported if A-reg != B-reg (all written Zeros and space between characters do not have detectable flux changes). On Tape Read operations, the TAU will report non high confidence data being received via a VRC error on the A-reg, but will then store the B-reg (lower threshold data) in memory and use it for LRC computation. So... VRC error and LRC error means that the record is corrupted. VRC error and no LRC error means that the record contains lower confidence data, but may be correct. (Useful for recovering data from aging tapes) LRC error and no VRC error means that the record was corrupted by having characters inserted and/or deleted in the record. On Tape Write operations, the TAU can not compare written data directly to read-back data because of the 1/4 second delay that occurs when the written data moves from the tape drive head's write- gap to the read-gap. Depending on the density being written, other characters may have been written in that delay interval. I wonder if other tape drive manufacturers designed their drives to insure high confidence data was written, but could recover more weakly written data from aging tapes. Regards, Bob

Subject - can IBM 7330 tape drives be connected to the IBM 1401 TAU (Tape Adaptor Unit)

From: Ignacio Menendez < ignalic @ yahoo . com > Date: Sat, Sep 30, 2017 6:40 pm Yes Robert, the 1401 TAU supported the 7330's, the ALD logics have plenty of circuits shown for 7330 or 729.

Subject: Re: the Stopped Clock From: Bob Feretich < bob.feretich@rafresearch.com > Date: Sun, Sep 11, 2016 6:33 pm To: ...

Microsecond oscillators... Read Clocks Write Clocks Osc. SMS Card SMS card ------ -------- ----------- 1 Mh TBV TDK 360KHz TBR TDG 667KHz TBS TDH 240KHz DAZ TDE 320KHz TB6 TDF 115KHz TBO TDD Write oscillators are ungated and crystal controlled. So start-up time is not a concern (they are always on). Read oscillators are gated by "First Bit" and LC controlled. Apparently the LC oscillators are expected to stabilize within a few cycles. Regards, Bob

On Sep 10, 2016, at 11:39 PM, Bob Feretich < bob.feretich@rafresearch.com > wrote:

The TAU is an independent unit that was developed separately and used in multiple IBM machines. The earlier version of the TAU was the TAU2. The 1401 used the TAU9. Its technology is different from the CPU. Still transistor oriented, but all logic gates are -6V to 0V. These gates weren't as fast as the CPU 12Vto0V; -6Vto+6V CPU alternating technology, nor did they have the same good noise margins, but the TAU didn't need the speed. (The lack of robust noise margin is a major cause of TAU card failure, the CPU cards can tolerate much more transistor leakage.) I think the technology generated what IBM called "S"-level outputs. The TAU is a big synchronous state machine. The TAU goes into "session" with one tape drive at a time. (I/O is not overlapped.) Based upon the tape drive model and density setting, two oscillators are selected. A "microsecond oscillator" and a "millisecond oscillator". > See the IBM Field Engineering Maintenance Manual 225-6487-3 page 149. Also, the flowcharts in this manual do a great job describing how the TAU works. The "microsecond oscillators" used are 115KHz, 240KHz, 320KHz, 360KHz, 667KHz, 960KHz, and 1MHz. These oscillators are used to perform bit level operations. (Bit recovery and transmission.) The "millisecond oscillators" are 6.67KHz and 10KHz. These oscillators are used to perform record level timings. (Reel start, stop, inter-record gaps and such.) Some logic (read and write counters) are clocked only by the "microsecond oscillators". Other logic (primarily the delay counter) are clocked by the mux of the microsecond and millisecond oscillators. The clock selection is based upon the part of the tape operation in progress. The CPU clocks do not enter the TAU, nor do the TAU clocks enter the CPU. Both clocks are present in the interface gate (between CPU and TAU), but luckily (for me) there was never a bug in this area, so I never explored it. >> In the TAU, the read state-machine oscillators are actually gated by a latch triggered by the "first one". So in between characters, the TAU read state machine clock is actually not oscillating. I recall a signal called "first bit" (I don't remember a "first one".). (See flow chart on page 147.) Between characters all data bits (and the check bit) should be unchanging (the tape flux is constant). Remember the tape encoding is NRZI, so no change is a logic zero. Therefore, all bits are 0s. "First bit" is an OR of the 7 tape tracks. I don't remember it starting any oscillators, but it does enable the microsecond oscillator clock into the "read counter" (a 4-bit synchronous counter in the TAU). When the read counter (RC) counts to 4, the A & B data latches open. They close on RC=7, it is required that data from all tracks is available at this time. This is the 7-track desqewing mechanism. All bits must arrive within 4-7 counts of the first bit. This clock gating occurs at the register level, not at the oscillator. I believe the gating at the oscillator is only used to at the beginning/end of a session (a Tape Read or Write instruction). Because of the mechanical delays, the oscillator has plenty of time to stabilize. The flowchart references RDD (Read Disconnect Delay). This is a use of the "Delay Counter", to detect a lack of flux transitions, indicating the end of the data part of a record and the impending arrival of the LRC character. The Tape Channel Analyzer Spec goes into great detail of these timings. ibm-1401.info/TapeXnalAnalyzerSpec_1_3.pdf Regards, Bob On 9/10/2016 6:36 PM, Grant Saviers wrote: My recollection, which in any case will be less the Bob's since he delved into the TAU logic more deeply, is that the crystal oscillators are free running. The TAU state machine gates different frequency crystal oscillators to a single (few?) counter to be able to derive different delays for use in the TAU. A pretty clever state machine design IMO, almost no pots or one shots. Re controlling CPU clocks, I have no data. Also, crystals have a start up time as they are essentially a very high Q tuned circuit driven with a feedback amplifier. In one design guide I found, a well designed oscillator at 10MHz took 67us to develop full amplitude, that is 670 clock cycles at a exponentially increasing amplitude. I think the more massive crystals for lower frequencies might take longer. That would be a very bad source for a gated clock signal. Usually, some shunt and series capacitance is used around a crystal to form the tuned circuit. An LC circuit might be added to reduce spurious (eg harmonic) frequencies. A well designed oscillator circuit with a specially cut crystal is about the lowest phase noise oscillator possible. Over to Bob... Grant

From: Guy Fedorkow < guy.fedorkow@gmail.com >
Subject: the Stopped Clock
Date: September 10, 2016 at 3:27:07 PM PDT
To: ...

So I actually did find the Stopped Clock in the tape drive logic... In the TAU, the read state-machine oscillators are actually gated by a latch triggered by the "first one". So in between characters, the TAU read state machine clock is actually not oscillating. This is done with a "gated oscillators", i.e. an oscillator that oscillates when the control signal is high, and stops when it's low. I can't say I've ever seen that before, and I still have a hard time believing the oscillator can start reliably on the first cycle, but it must be true. The oscillators themselves seem to be LC-stabilized, not crystal oscillators. And as Iggy said, wow, there are a lot of them, with different oscillators for every combination of tape density and drive type. http://ibm-1401.info/ALDs-VSnyder-Australia/7_7/805537.pdf http://files.righto.com/sms/TBV.html But I'm still sure that the tape controller does not 'take over' the 1401 clock, although I think it does cause the 1401 clock state machine to stall waiting for the next character. ya never know what you're gonna find... /guy